STV1601A datasheet(11/17 Pages) STMICROELECTRONICS

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Figure 9 : tr,tf Definition

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Figure 10 : td,tW Definition

DESCRIPTION

STV1601A internally generates a 10 times clock

frequency locked to the parallel input clock thanks

to a built-in PLLand converts input parallel data into

serial data.

To ease clock extraction at the receiving end, serial

data is scrambled. To minimize polarity effect, serial

data is then converted to NRZI and output in differ-

ential mode.

A PLL lock detection circuit only enables the serial

output when locked.

1. Phase relation between input parallel clock

and data

The phase relation between the parallel clock and

the data is shown in Figure 11. Both clock and data

are differential inputs

Parallel clock and data are such that the rising edge

of PCX should be at the middle of the data. A clock

having the same phase as PCX is internally gener-

ated in order to latch the data.

2. TTL input operation

Parallel clock and data can be either TTL or ECL

inputs. To use as TTL inputs VCC (Pin 29) shall be

connected to +5V. A fixed bias of +1.4V shall be

applied to PCY and DnY (n = 0 to 9). TTL signals

and their parallel clock will be provided through

1kW resistors to each ”X” input. These 1kW resis-

tors are effective to minimize the influence of the

TTL input signals to the jitter characteristics of the

serial output signal. For 8-bit data, unused LSB(s)

must be fixed Low. Fixed bias value can be higher,

for example, 2.5V in case of CMOS inputs.

PCX (Input)

DATA (Input)

PCX (Output)

Figure 11 : Phase Relation between Clock and Data

Parallel

Clock

Parallel

Data

+5V

+ 1.4V for TTL

+ 2.5V for CMOS

D0Y

D0X

D9Y

D9X

PCY

PCX

TTL Parallel Signal

STV1601A

Ω

Figure 12 : TTL Input Operation

STV1601A

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