STV0299B datasheet(15/36 Pages) STMICROELECTRONICS

15 / 36 page

STV0299B

15/36

FUNCTIONAL DESCRIPTION (continued)

4.6 Forward Error Correction

4.6.1

FEC Modes

Since the STV0299B is a multistandard decoder,

several combinations are possible, at different

levels:

• The demodulator may accept either QPSK or

BPSK signals - the only impact is on the carrier

algorithm choice (refer to Chapter 4.4).

The algorithm choice also affects the carrier

lock detector and the noise evaluation.

• There two primary options concerning the FEC

operation - between DVB, DSS and Reserved

Mode.

• There are two options concerning the FEC

feeding. The first is IQ flow, which is the usual

case in QPSK modes DVB or DSS. The second

mode is I-only flow, used for BPSK.

The FEC Mode Register is in Address 28.

In Modes DVB and DSS, data is fed to the Viterbi

decoder. Other parts of the decoding (such as the

Convolutional Deinterleaver) may be bypassed.

4.6.2

Viterbi Decoder and Synchronization

The convolutive codes are generated by the

polynomial Gx = 171 octets and Gy = 133 octets in

modes DVB or DSS.

The Viterbi decoder computes for each symbol

the metrics of the four possible paths, proportional

to the square of the Euclidian distance between

the received I and Q and the theoretical symbol

value.

The puncture rate and phase are estimated on the

error rate basis. Several rates are allowed and

may

enabled/disabled

through

programming:

• 1/2, 2/3, 3/4, 5/6, 7/8 in DVB.

• 1/2, 2/3, 3/4, 5/6 and 6/7 in DSS.

For each enabled rate, the current error rate is

compared to a programmable threshold. If it is

greater than this threshold, another phase (or

another rate) is tried until the right rate is obtained.

A programmable hysteresis is added to avoid

losing the phase during short term perturbation.

The rate may also be imposed by external

software, and the phase is incremented only upon

request by the microprocessor. The error rate may

be read at any time in order to use an algorithm

other than that implemented.

The

Viterbi

decoder

produces

absolute

decoding. The decoder is controlled via several

Viterbi Threshold Registers (Registers 29, 2A, 2B,

2C and 2D). For each Viterbi Threshold Register,

bits 6 to 0 represent an error rate threshold - the

average number of errors occurring during 256-bit

periods. The maximum programmable value is

127/256 (higher error rates are of no practical

use).

The Puncture Rate and Synchro Register is in

Address 31.

The automatic rate research is only done through

the enabled rates (see the corresponding bit set in

the Puncture and synchro register). In DSS, the

puncture rate 6/7 replaces the puncture rate 7/8.

In DSS, it is recommended that you disable

puncture rates 3/4 and 5/6 in order to save time in

the synchronization process.

The VSEARCH Register is in Address 32.

VSEARCH bit 7 (A/M) and bit 6 (F) programs the

automatic/manual (or computer aided) search

mode as follows:

• If A/M =0 and F=0, automatic mode is set.

Successive enabled punctured rates are tried

with all possible phases, until the system is

locked and the block synchro found. This is the

default (reset) mode.

• If A/M=0 and F=1, the current puncture rate is

frozen. If no sync is found, the phase is

incremented,

but

not

the

rate

number.

This mode allows shortening of the recovery

time in case of noisy conditions. The puncture

rate is not supposed to change in a given

channel.

typical

computer-aided

implementation,

the

research

begins

automatic mode. The microprocessor reads the

error rate or the PRF flag in order to detect the

capture of a signal, then it switches F to 1, until

a new channel is requested by the remote

control.

• If AM=1 manual mode is set. In this case, only

one puncture rate should be validated -

the system is forced to this rate, on the current

phase, ignoring the time-out register and the

error rate. In this mode, each 0 to 1 transition of

the bit F leads to a phase incrementation,

allowing full control of the operation by an

external microprocessor by choosing the lowest

error rate.

The reset values are A/M=0, and F=0 (automatic

search mode).

The VERROR Register (a read only register) is in

Address 26. The last value of the error rate may

be read at any time in the register. Unlike the VTH,

the possible range is from 0 to 255/256.

The VSTATUS Register (a read only register) is in

Address 1B.

STV0299B датащи(PDF) 15 Page - STMicroelectronics

STV0299B датащи(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL