I

Symbol

Parameter

Test Conditions

Min.

Typ. Max.

Unit

Input Logic Low Voltage

Input Logic High Voltage

See Note 1

-0.3

2.0

0.8

5.5

V

V

Output Logic Low Voltage

Output Logic High Voltage

M_CLK = 60MHz, see Note 1

2.4

0.5

5.5

V

V

Input Leakage Current

-10

10

µA

Input Capacitance

3.5

pF

Output Sink Current

10

mA

Pulse W idt h of Spikes which must be

suppressed by the Input filter

050

ns

SCL Clock Frequency

0

400

kHz

Bus Free Time between a STOP and START

Condition

1.3

µs

Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated.

0.6

µs

Low Period of the SCL Clock

High Period of the SCL Clock

1.3

0.6

µs

µs

Set-up Time for a repeated START Condition

0.6

µs

Set-up Time for STOP Condition

0.6

µs

Data Hold Time

See Note 3

0

0.9

µs

Data Set-up Time

See Note 4

100

ns

Rise and Fall Time of both SDA and SCL

signals

See Note 5

20 +

300

ns

Capacitive Load for each Bus Line

400

pF

Notes : 1.

An impedance higher than 2k

Ω is required when SDA and SCL are tied to a 5V ± 10% voltage line.

2.

Leakage current exceeds

± 10µA when SDA and SCL are tied to a 5V ± 10% line.

3.

to bridge the undefined region of the falling edge of SCL.

4.

A fast-mode I

≥ 250ns must then be

met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does

(according to the standard-mode I

5.

STV0196B

15/23