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M37151EFFP датащи(PDF) 9 Page - Renesas Technology Corp |
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M37151EFFP датащи(HTML) 9 Page - Renesas Technology Corp |
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9 / 138 page ![]() M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 9 of 136 REJ03B0129-0100Z Ports P1, P2, P30, P31 Data bus Ports P00–P07 Data bus Port latch Direction register Port latch Direction register Fig. 7.1 I/O Pin Block Diagram (1) N-channel open-drain output Ports P00–P07 Note : Each port is also used as follows : P00–P04 : PWM0–PWM4 P05: AD3 P06: INT2/AD4 P07: INT1 CMOS output Ports P1, P2, P30, P31 Notes 1 : Each port is also used as follows : P10 : CLKCONT P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 P16 : AD8/TIM2 2: The output structure of ports P11–P14, P30–P31 is N-channel open-drain output when using as multi-master I2C-BUS interface (it is the same with P00–P07). 3: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (it is the same as P00–P07). P20 : SCLK/AD5 P21 : SOUT/AD6 P22 : SIN/AD7 P23 : TIM3 P24 : TIM2 P25 : INT3 P26 : XCIN P27 : XCOUT P30 : SDA3 P31 : SCL3 |
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