7477 datasheet(15/48 Pages) RENESAS

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MITSUBISHI MICROCOMPUTERS

7477/ 7478 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMER

The 7477/7478 group has four timers; timer 1, timer 2, timer 3,

and timer 4.

A block diagram of timer 1 through 4 is shown in Figure 6.

Timer 1 can be operated in the timer mode, event count mode, or

pulse output mode. Timer 1 starts counting when bit 0 in the timer

12 mode register (address 00F816) is set to “0”.

The count source can be selected from the f(XIN) divided by 16,

f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR0 pin.

Do not select f(XCIN) as the count source in the 7477 group. When

bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided

by 16 or f(XCIN) divided by 16 is selected. Selection between

f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (ad-

dress 00FB16). When bit 1 in the timer 12 mode register is “0” and

bit 2 is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12

mode register is “1”, an event input from the CNTR0 pin is se-

lected. Event inputs are selected depending on bit 2 in the edge

polarity selection register (address 00D416). When this bit is “0”,

the inverted value of CNTR0 input is selected; when the bit is “1”,

CNTR0 input is selected.

When bit 3 in the timer 12 mode register is set to “1”, the P12 pin

becomes timer output T0. When the direction register of P12 is set

for the output mode at this time, the timer 1 overflow divided by 2

is output from T0.

Please set the initial output value in the following procedure.

Set “1” to bit 0 of the timer 12 mode register.

(Timer 1 count stop.)

Set “1” to bit 0 of the timer mode register 2.

Set the output value to bit 0 of the timer FF register.

Set the count value to the timer 1.

Set “0” to bit 0 of the timer 12 mode register.

(Timer 1 count start.)

Timer 2 can only be operated in the timer mode. Timer 2 starts

counting when bit 4 in the timer 12 mode register is set to “0”.

The count source can be selected from the divide by 16, divide by

64, divide by 128, or divide by 256 frequency of f(XIN) or f(XCIN),

and timer 1 overflow. Do not select f(XCIN) as the count source in

the 7477 group. When bit 5 in the timer 12 mode register is “0”,

any of the divide by 16, divide by 64, divide by 128, or divide by

256 frequency of f(XIN) or f(XCIN) is selected. The divide ratio is

selected according to bit 6 and bit 7 in the timer 12 mode register,

and selection between f(XIN) and f(XCIN) is made according to bit

7 in the CPU mode register. When bit 5 in the timer 12 mode reg-

ister is “1”, timer 1 overflow is selected as the count source.

Timer 3 can be operated in the timer mode, event count mode, or

PWM mode. Timer 3 star ts counting when bit 0 in the timer 34

mode register (address 00F916) is set to “0”.

The count source can be selected from the f(XIN) divided by 16,

f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an

event input from P33/CNTR1 pins according to the statuses of bit 1

and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg-

ister 2 (address 00FA16) and bit 7 in the CPU mode register. Do

not select f(XCIN) as the count source in the 7477 group. Note,

however, that if timer 1 overflow or timer 2 overflow is selected for

the count source of timer 3 when timer 1 overflow is selected for

the count source of timer 2, timer 1 overflow is always selected re-

gardless of the status of bit 6 in the timer mode register 2. Event

inputs are selected depending on bit 3 in the edge polarity selec-

tion register. When this bit is “0”, the inverted value of CNTR1 input

is selected; when the bit is “1”, CNTR1 input is selected.

Timer 4 can be operated in the timer mode, event count mode,

pulse output mode, pulse width measuring mode, or PWM mode.

Timer 4 starts counting when bit 3 in the timer 34 mode register is

set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the

pulse width measuring mode is selected. The count source can be

selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN) divided

by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from

P33/CNTR1 pin according to the statuses of bit 4 and bit 5 in the

timer 34 mode register, bit 6 in the timer mode register 2, and bit 7

in the CPU mode register. Do not select f(XCIN) as the count

source in the 7477 group. Note, however, that if timer 1 overflow or

timer 2 overflow is selected for the count source of timer 4 when

timer 1 overflow is selected for the count source of timer 2, timer 1

overflow is always selected regardless of the status of bit 6 in the

timer mode register 2. Event inputs are selected depending on bit

3 in the edge polarity selection register.

When this bit is “0”, the inverted value of CNTR1 input is selected;

when the bit is “1”, CNTR1 input is selected.

When bit 7 in the timer 34 mode register is set to “1”, the P13 pin

becomes timer output T1. When the direction register of P13 is set

for the output mode at this time, the timer 4 overflow divided by 2

is output from T1 when bit 7 in the timer mode register 2 is “0”.

Please set the initial output value in the following procedure.

Set “1” to bit 3 of the timer 34 mode register.

(Timer 4 count stop.)

Set “1” to bit 1 of the timer mode register 2.

Set the output value to bit 1 of the timer FF register.

Set the count value to the timer 4.

Set “0” to bit 3 of the timer 34 mode register.

(Timer 4 count start.)

(1) Timer mode

Timer performs down count operations with the dividing ratio being

1/(n+1). Writing a value to the timer latch sets a value to the timer.

When the value to be set to the timer latch is nn16, the value to be

set to a timer is nn16, which is down counted at the falling edge of

the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 0016

to FF16. At the falling edge of the count source immediately after

timer value has reached FF16, value (nn16-1) obtained by subtract-

ing one from the timer latch value is set (reloaded) to the timer to

continue counting. At the rising edge of the count source immedi-

ately after the timer value has reached FF16, an overflow occurs

and an interrupt request is generated.

(2) Event count mode

Timer operates in the same way as in the timer mode except that

it counts input from the CNTR0 or CNTR1 pin.

(3) Pulse output mode

In this mode, duty 50% pulses are output from the T0 or T1 pin.

When the timer overflows, the polarity of the T0 or T1 pin output

level is inverted.

(4) Pulse width measuring mode

The 7477/7478 group can measure the “H” or “L” width of the

CNTR0 or CNTR1 input waveform by using the pulse width mea-

suring mode of timer 4. The pulse width measuring mode is

selected by writing “1” to bit 6 in the timer 34 mode register. In the

pulse width measuring mode, the timer counts the count source

while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0

input or CNTR1 input to be measured can be specified by the sta-

tus of bit 4 in the edge polarity selection register; whether the “H”

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