38C3 datasheet(49/63 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

38C3 Group

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK)

twH(SCLK)

twL(SCLK)

tsu(SIN-SCLK)

th(SCLK-SIN)

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0–INT2 input “H” pulse width

INT0–INT2 input “L” pulse width

Serial I/O clock input cycle time

Serial I/O clock input “H” pulse width

Serial I/O clock input “L” pulse width

Serial I/O input setup time

Serial I/O input hold time

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK)

twH(SCLK)

twL(SCLK)

tsu(SIN-SCLK)

th(SCLK-SIN)

Limits

µs

Parameter

Min.

125

250

105

800

370

220

100

Typ.

Max.

Symbol

Unit

Limits

µs

Parameter

Min.

125

500/(VCC–2)

250/(VCC–2)–20

230

2000

950

400

200

Typ.

Max.

Symbol

Unit

Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0–INT2 input “H” pulse width

INT0–INT2 input “L” pulse width

Serial I/O clock input cycle time

Serial I/O clock input “H” pulse width

Serial I/O clock input “L” pulse width

Serial I/O input setup time

Serial I/O input hold time

Table 19 Timing requirements 2 (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)

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