HD404328FS datasheet(9/103 Pages) RENESAS

9 / 103 page

HD404054 Series/HD404094 Series

$000

576

960

1023

$040

$050

$003

$004

$005

$006

$007

$008

$009

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$020

$023

$032

$033

$034

$035

$03F

$00E

$00F

R/W

$3C0

$240

RAM-mapped registers

Memory registers (MR)

Data (432 digits)

Stack (64 digits)

Interrupt control bits area

Port mode register A

Serial mode register 1A

Serial data register 1 lower

Serial data register 1 upper

Timer mode register A

Miscellaneous register

Timer mode register C1

Timer C

Timer mode register D2

Port R0 DCR

Port R1 DCR

Port R2 DCR

Port R3 DCR

Port D to D DCR

Port D and D DCR

Timer read register C lower

Timer read register C upper

Timer write register C lower

Timer write register C upper

$090

R/W:

Read only

Write only

Read/Write

$011

$012

Timer read register D lower

Timer read register D upper

Timer write register D lower

Timer write register D upper

144

Timer mode register D1

R/W

Timer D

Timer mode register C2

$015

$016

Compare data register

$017

$024

$025

$026

$027

$028

$029

$02A

$02B

$018

$019

$01F

$3FF

Compare enable register

Port mode register B

Port mode register C

Detection edge select register 2

Serial mode register 1B

Port R4 DCR

$02C

$02D

$02E

$02F

$031

$030

Two registers are mapped

on the same area.

R/W

(PMRA)

(SM1A)

(SR1L)

(SR1U)

(TMA)

(MIS)

(TMC1)

(TRCL/TWCL)

(TRCU/TWCU)

(TMD1)

(TRDL/TWDL)

(TRDU/TWDU)

(TMC2)

(TMD2)

(CDR)

(CER)

(PMRB)

(PMRC)

(SM1B)

(ESR2)

(DCD0)

(DCD1)

(DCD2)

(DCR0)

(DCR1)

(DCR2)

(DCR3)

(DCR4)

(TRCL)

(TRCU)

(TRDL)

(TRDU)

(TWCL)

(TWCU)

(TWDL)

(TWDU)

Not used

Figure 2 RAM Memory Map

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