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HD404618TF датащи(PDF) 57 Page - Renesas Technology Corp |
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HD404618TF датащи(HTML) 57 Page - Renesas Technology Corp |
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57 / 91 page ![]() HD404618 Series 55 Transmission completion (IFS 1) ← Interrupts inhibited IFS 0 ← SMR write IFS = 1 ? Normal termination Transmit clock error processing No Yes Figure 34 Transmit Clock Error Detection Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the execution of an SMR write or STS instruction during the first period that the transmit clock is low. To prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port) before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is set. |
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