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HD404324FS датащи(PDF) 20 Page - Renesas Technology Corp

номер детали HD404324FS
подробное описание детали  microcomputer designed to increase program productivity
PDF  103 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404324FS датащи(HTML) 20 Page - Renesas Technology Corp

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HD404054 Series/HD404094 Series
18
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
INT
0
INT
1
Timer A
Timer C
Timer D
Serial 1
IE
11
1111
IF0 ·
IM0
10
0000
IF1 ·
IM1
*
1
0000
IFTA ·
IMTA
**
1000
IFTC ·
IMTC
**
*
100
IFTD ·
IMTD
**
**
10
IFS1 ·
IMS1
**
***
1
Note:
* Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
12
3
4
5
6
Instruction
execution
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note:
The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
*
Stacking
*
Figure 9 Interrupt Processing Sequence



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