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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38045F2HKP датащи(PDF) 59 Page - Renesas Technology Corp |
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M38045F2HKP датащи(HTML) 59 Page - Renesas Technology Corp |
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59 / 116 page  Rev.1.01 Jan 25, 2005 page 59 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ= 4 MHz) Table 7 Multi-master I2C-BUS interface functions Item Format Communication mode System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) MULTI-MASTER I2C-BUS INTERFACE The 3804 group (Spec. H) has the multi-master I2C-BUS interface. The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. Figure 56 shows a block diagram of the multi-master I2C-BUS in- terface and Table 7 lists the multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C slave ad- dress registers 0 to 2, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C START/STOP condition control register, the I2C special mode control register, the I2C special mode status register, and other control circuits. When using the multi-master I2C-BUS interface, set 1 MHz or more to the internal clock φ. Fig. 56 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SCL clock frequency I2C status register b7 b0 SAD6SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB b7 b0 b7 MST TRX BB PIN AL AAS AD0 LRB b0 S1 BB circuit b7 b0 ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 S0 S2 S0D0–2 SIS I2C START/STOP condition control register SIP SSC4 SSC3 SSC2 SSC1SSC0 b7b0 TISS TSEL 10BIT SAD ALS BC2BC1 BC0 S1D ES0 b7b0 SPCF S3 PIN2 AAS2AAS1AAS0 b7b0 SPCFL S3D PIN2 HD PIN2 IN HSLAD ACKI CON I2 C special mode control register I2C special mode status register I2C slave address registers 0 to 2 Noise elimination circuit Address comparator Data control circuit System clock ( φ) Interrupt generating circuit Interrupt request signal (I2CIRQ) Bit counter Clock control circuit Internal data bus Clock division AL circuit I2C clock control register I2C control register Serial clock (SCL) I2C data shift register Interrupt request signal ( SCL, SDA, IRQ) Interrupt generating circuit Serial data (SDA) Noise elimination circuit S2D |
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