поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

4282 датащи(PDF) 39 Page - Renesas Technology Corp

номер детали 4282
подробное описание детали  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  69 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4282 датащи(HTML) 39 Page - Renesas Technology Corp

Back Button 4282 Datasheet HTML 35Page - Renesas Technology Corp 4282 Datasheet HTML 36Page - Renesas Technology Corp 4282 Datasheet HTML 37Page - Renesas Technology Corp 4282 Datasheet HTML 38Page - Renesas Technology Corp 4282 Datasheet HTML 39Page - Renesas Technology Corp 4282 Datasheet HTML 40Page - Renesas Technology Corp 4282 Datasheet HTML 41Page - Renesas Technology Corp 4282 Datasheet HTML 42Page - Renesas Technology Corp 4282 Datasheet HTML 43Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 69 page
background image
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Rev.1.33
Mar 18, 2004
page 39 of 67
4282 Group
TAB1 (Transfer data to Accumulator and register B from timer 1)
001010111
057
11
Grouping:
Timer operation
Description: Transfers the contents of timer 1 to regis-
ters A and B.
Operation:
(B)
← (T17–T14)
(A)
← (T13–T10)
TABE (Transfer data to Accumulator and register B from register E)
000101010
02A
11
Grouping:
Register to register transfer
Description: Transfers the contents of register E to reg-
isters A and B.
Operation:
(B)
← (ER7–ER4)
(A)
← (ER3–ER0)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
01001p3
p2
p1
p0
09p
13
0/1
Grouping:
Arithmetic operation
Description:
Transfers bits 7 to 4 to register B and bits 3 to 0 to register
A when URS flag is cleared to “0.” These bits 7 to 0 are the
ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) speci-
fied by registers A and D in page p.
Transfers bit 8 of ROM pattern is transferred to flag CY when
URS flag is set to “1” (after the URSC instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
Operation:
SK(SP))
← (PC) , (SP) ← (SP) + 1
(PCH)
← p, p = 0 to 7, (PCL) ← (DR2–DR0, A3–A0)
When URS = 0,
(B)
← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
When URS = 1,
(CY)
← (ROM(PC))8
(B)
← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
(SP)
← (SP) – 1, (PC) ← (SK(SP))
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
TAB2 (Transfer data to Accumulator and register B from timer 2)
001000000
040
11
Grouping:
Timer operation
Description: Transfers the contents of timer 2 to regis-
ters A and B.
Operation:
(B)
← (T27–T24)
(A)
← (T23–T20)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com