455A datasheet(29/148 Pages) RENESAS

29 / 148 page

Rev.1.01

Feb 15, 2008

Page 29 of 146

REJ03B0224-0101

455A Group

(3) Notes on interrupts

(1) Bit 3 of register I1

When the input of the INT pin is controlled with the bit 3 of

• Depending on the input state of the D5/INT pin, the external 0

interrupt request flag (EXF0) may be set when the bit 3 of

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer

to (1) in Figure 29.) and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0

flag to “0” after executing at least one instruction (refer to (2)

in Figure 29.).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ0 instruction (refer to (3) in Figure

29.).

Fig 29. External 0 interrupt program example-1

(2) Bit 3 of register I1

When the bit 3 of register I1 is cleared to “0”, the power

down mode is selected and the input of INT pin is disabled,

be careful about the following notes.

• When the INT pin input is disabled (register I13 = “0”), set the

key-on wakeup of INT pin to be invalid (register K20 = “0”)

before system enters to power down mode. (refer to (1) in

Figure 30.).

Fig 30. External 0 interrupt program example-2

(3) Bit 2 of register I1

When the interrupt valid waveform of the INT pin is

changed with the bit 2 of register I1 in software, be careful

about the following notes.

• Depending on the input state of the D5/INT pin, the external 0

interrupt request flag (EXF0) may be set when the bit 2 of

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer

to (1) in Figure 31.) and then, change the bit 2 of register I1 is

changed.

In addition, execute the SNZ0 instruction to clear the EXF0

flag to “0” after executing at least one instruction (refer to (2)

in Figure 31.).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ0 instruction (refer to (3) in Figure

31.).

Fig 31. External 0 interrupt program example-3

•

LA 4

; (

×××02)

TV1A

; The SNZ0 instruction is valid ...... (1)

LA 8

; (1

×××2)

TI1A

; Control of INT pin input is changed

NOP

...................................................... (2)

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

...................................................... (3)

•

×: these bits are not used here.

•

LA 0

; (

×××02)

TK2A

; INT0 key-on wakeup disabled .....(1)

EPOF

POF2

; RAM back-up

•

×: these bits are not used here.

•

LA 4

; (

×××02)

TV1A

; The SNZ0 instruction is valid ......(1)

LA 12

; (

×1××2)

TI1A

; Interrupt valid waveform is changed

NOP

.......................................................(2)

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

.......................................................(3)

•

×: these bits are not used here.

455A датащи(PDF) 29 Page - Renesas Technology Corp

455A датащи(HTML) 29 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL