Rev.3.00, Jul.15.2005, page 1 of 6

HD74LS273

Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

REJ03D0473–0300

Rev.3.00

Jul.15.2005

The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a

direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going

edge of the clock pulse.

When the clock input is at either the high or low level, the D input signal has no effect at the output.

Features

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LS273P

DILP-20 pin

PRDP0020AC-B

(DP-20NEV)

P

—

HD74LS273FPEL

SOP-20 pin (JEITA)

PRSP0020DD-B

(FP-20DAV)

FP

EL (2,000 pcs/reel)

HD74LS273RPEL

SOP-20 pin (JEDEC)

PRSP0020DC-A

(FP-20DBV)

RP

EL (1,000 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Pin Arrangement

(Top view)

GND

Clear

1Q

1D

2D

2Q

3Q

3D

4D

4Q

8Q

7D

8D

7Q

6D

6Q

5D

Clock

5Q

20

17

18

19

15

16

1

2

3

4

5

6

7

14

8

9

10

11

12

13

Q

DCK

Clear

Q

DCK

Clear

Q

D

CK

Clear

Q

D

CK

Clear

Q

DCK

Clear

Q

DCK

Clear

Q

D

CK

Clear

Q

D

CK

Clear