HD74LS195A

Rev.3.00, Jul.15.2005, page 6 of 7

Waveform

Clear

Clock

Data

Shift/Load

Outputs Q

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

0V

3V

0V

3V

0V

3V

0V

3V

10%

10%

10%

10%

90%

90%

90% 90%

Notes:

1.

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz, duty cycle 50%

2.

A clear pulse is applied prior to each test.

3.

4.

J and

K inputs are tested the same as data A, B, C, and D inputs except that shift / load input

remains high.

5.

6.

7.