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HD74LVC2G66 датащи(PDF) 8 Page - Renesas Technology Corp |
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HD74LVC2G66 датащи(HTML) 8 Page - Renesas Technology Corp |
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8 / 12 page ![]() HD74LVC2G66 Rev.3.00 Jul 07, 2005 page 8 of 11 Test Circuit (cont.) OPEN OPEN TEST S1 VTT VTT S1 CL RL RL GND GND t / t PLH PHL t / t ZH HZ t / t ZL LZ 1.8±0.15 2.5±0.2 3.3±0.3 5.0±0.5 INPUTS VCC (V) VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC VCC / 2 VCC / 2 VCC / 2 VCC / 2 VCC VCC VCC VI Vref CL RL ∆V VTT tr / tf 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V 500 Ω 500 Ω 1.0 k Ω Load circuit From Output ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns 30 pF 30 pF 50 pF 50 pF Vref Vref Vref Vref VI 0 V t PLH V t PHL OH VOL Input Output VOH VOL Control Input Vref Vref Vref VOH – ∆V VOL + ∆V Vref VI VOH 0 V VOL t HZ t LZ t ZH t ZL Output (Waveform – A) Output (Waveform – B) Notes: 1. CL includes probe and jig capacitance. 2. Waveform–A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform–B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50 Ω. 5. The output are measured one at a time with one transition per measurement. |
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