Analog Integrated Circuit Device Data

24

Freescale Semiconductor

33879

REVISION HISTORY

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

5.0

2/2006

•

Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block

diagram.

•

Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition.

•

Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD

Supply contains no hysteresis.

•

Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max

parameter has been increased from 70uA to 90uA.

•

Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been

updated to reflect the voltage of the VPWR pin during the parameter test.

•

Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been

updated to reflect the voltage of the VPWR pin during the parameter test.

•

Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter

has been decreased from 7uA to 5uA.

•

Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin.

•

Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right.

•

ALL Pages; Updated Data Sheet to reflect Freescale formatting.

6.0

6/2007

•

Added 33879A version

•

Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information

•

Added Device Variations on page 2

•

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Maximum Rations on page 6. Added note with instructions from www.freescale.com.

•

Changed Output Fault Detection Voltage Threshold(7) on page 8

•

Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on page 14

•

Changed Overvoltage on page 18 and Overvoltage Fault on page 19

7.0

8/2008

•

Updated package drawing.