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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VIPER17_0810 датащи(PDF) 23 Page - STMicroelectronics |
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VIPER17_0810 датащи(HTML) 23 Page - STMicroelectronics |
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23 / 33 page  VIPER17 Operation descriptions 23/33 Equation 7 Equation 8 The RFB(DYN) is the dynamic resistance seen by the FB pin. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike. Figure 28. FB pin configuration Figure 29. FB pin configuration () 1 FB ) DYN ( FB FB 1 FB ) DYN ( FB PFB R R C 2 R R f ⋅ ⋅ ⋅ π ⋅ + = () ) DYN ( FB 1 FB 1 FB 1 PFB R R C 2 1 f + ⋅ ⋅ π ⋅ = From sense FET 4.8V BURST PWM CONTROL Cfb To PWM Logic BURST-MODE REFERENCES BURST-MODE LOGIC + - PWM + - OLP comparator To disable logic 4.8V From sense FET PWM CONTROL + - PWM BURST To disable logic + - OLP comparator To PWM Logic BURST-MODE LOGIC Cfb1 Rfb1 Cfb BURST-MODE REFERENCES |
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