© 1997 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FST3245 • Rev. 1.0.2

6

Physical Dimensions

0.10 C

C

A

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

1

10

B

CA

M

20

11

B

X 45°

8°

0°

SEATING PLANE

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.65

1.27

2.25

9.50

13.00

12.60

11.43

7.60

7.40

10.65

10.00

0.51

0.35

1.27

2.65 MAX

0.30

0.10

0.33

0.20

0.75

0.25

(R0.10)

(R0.10)

1.27

0.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide

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