STPCI0180BTC3 datasheet(13/55 Pages) STMICROELECTRONICS

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STRAP OPTION

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Issue 1.1

2.1.2 STRAP REGISTER 1 INDEX 4BH (STRAP1)

Bits 7-0, This register reflect the status of pins MD[15:8] respectively. They are expected to be connected

on the system board to the SIMM configuration pins as follows:

Note that the SIMM speed and type information read here is meant only for the software and is not used

by the hardware. The software must program the Host and graphics dram controller configuration regis-

ters appropriately based on these bits.

This register defaults to the values sampled on MD[15:8] pins after reset.

2.1.3 STRAP REGISTER 2 INDEX 4CH (STRAP2)

Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta-

tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect.

They are use by the chip as follows:

Bits 7-5, Reserved

Bit 4, This bit reflects the value sampled on MD[20] pin and controls the Dot clock (DCLK) source. Note

this bit is writeable as well as readable.

Bit 3, This bit reflects the value sampled on MD[19] pin and controls the Graphics clock source.

Bit 2, This bit reflects the value sampled on MD[18] pin and controls the Host/CPU clock source as fol-

lows: setting to ’0’: External. HCLK pin is an input, setting to ’1’: Internal. HCLK pin is an output and is con-

nected to the internal frequency synthesizer output.

Bit 1, This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows:

Setting to ’0’, the PCI clock output = HCLK / 3

Setting to ’1’, the PCI clock output = HCLK / 2

Bit 0, Reserved.

This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset.

Bit Sampled

Description

Bit 7

SIMM 2 DRAM type

Bits 6-5

SIMM 2 speed

Bit 4

SIMM 3 DRAM type:

Bits 3-2

SIMM 3 speed

Bit 1-0

Reserved

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