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VT5366 датащи(PDF) 18 Page - STMicroelectronics

номер детали VT5366
подробное описание детали  1.8V optical mouse sensor
PDF  30 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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VT5366 датащи(HTML) 18 Page - STMicroelectronics

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Serial control bus
VT5366
18/30
6
Serial control bus
6.1
General description
The 2-wire I2C serial interface bus is used to read and write the VT5366 registers.
The main features of the serial interface include:
–
Variable length read/write messages
–
Indexed addressing of information source or destination within the sensor
–
Automatic update of the index after a read or write message
–
Message abort with negative acknowledge from the master
–
Byte oriented messages
6.2
Serial communication protocol
The co-processor must perform the role of communication ‘master’ and the sensor acts as a
‘slave’. The communication from host to sensor takes the form of 8-bit data with a maximum
serial clock frequency of 400 kHz. Since the serial clock is generated by the bus master it
determines the data transfer rate. Data transfer protocol on the bus is illustrated in
Figure 7.
Figure 7.
Serial Interface data transfer protocol
6.2.1
Data format
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The
internal data is produced by sampling
sda at a rising edge of scl. The external data must be
stable during the high period of
scl. Exceptions to this are start (S) or stop (P) conditions
when
sda falls or rises respectively, while scl is high.
A message contains at least two bytes. Its begins with a
start condition and ends with either
a
stop condition or another start condition In this situation the (second) start is referred to as
a
repeated start and is shown as (Sr). The first byte of a transaction always contains the
device address byte in the upper 7 bits with the LSB indicating the data direction; 1 for
read
or 0 write. Thus the 8 bit device address for the VT5366 is 0x20 for writing and 0x21 for
reading.
Figure 8.
VT5366 serial interface address
12
7
8
A
Start condition
Stop condition
SDA
SCL
Acknowledge
P
S
3
4
56
Address or data byte
MSB
LSB
0
0
1
0
0
0
0
R/W



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