STW8009 datasheet(46/66 Pages) STMICROELECTRONICS

46 / 66 page

STw8009/STw8019

Control registers

45/65

5.2.2

Control & power management unit registers

Control and power management unit

standby: In this mode the analog subsystem is supplied by the 1.2V/1.4V and the

2.8V/3.3V, but the DACs are set in power down mode, via poff[1:2] bits (Reg 130 & 131).

Digital to analog data conversion is disabled.

(*) 0 = disabled (active mode)

1 = standby

Control and power management unit reset

cpmuswrst: Control and power management unit reset

(*) 0 = disabled

1 = control and power management unit software reset

Note:

Bit cpmuswrst is automatically reset to its default value after internal reset generation and

the I2C data transfer is stopped. This reset is kept available for a CLK cycle.

poff1: DAC2 power off, then turn off DAC2 is in a low power consumption mode

0 = disabled (DAC2 active)

(*) 1 = turned off

Note:

As Default value is “1”, Digital processor must write “0” when going from sleep or standby to

active mode.

notzerod1 : null digital data inputed on DAC2

0 = independently of what is coming from the digital part, “0000000000” is forced on

DAC2 input.

(*) 1 = disabled, values issued from DENC are transmitted to DAC2.

pedestalOnd1 : Black level video pedestal active on DAC2

(*) 0 = disabled

1 = video pedestal active

Configuration0

Address:

0x0080

Type: R/W

content

standby

default

0000

Configuration 1

Address:

0x0081

Type: R/W

content

cpmuswrst

default

000

DAC1 control

Address:

0x0082

Type: R/W

content

poff1

notzerod1

pedestal

Ond1

default

000

STW8009 датащи(PDF) 46 Page - STMicroelectronics

STW8009 датащи(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL