STV2310 datasheet(58/112 Pages) STMICROELECTRONICS

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STV2310

58/112

5.2

Non-VBI Control Register Descriptions

DDECCONT0

DDECCONTF

7Eh

0000 0000

INTERDET

_ACK

VCRDET_

ACK

INSERDET

_ACK

FBDET_AC

PLLLOCK_

ACK

VLOCK_A

HLOCK_A

TVSTDID_

ACK

DDECCONTF

7Fh

0000 0000

VSYNCNS

TD_ACK

TRICKDET

_ACK

DDECSTAT1

80h

0001 0000

STVDDECVERS[7:0]

DDECSTAT2

81h

READ ONLY

VLOCK

HLOCK

PLLLOCK

5060ID

TVSTDID

TVSTD[2:0]

DDECSTAT3

82h

READ ONLY

VSYNCLO

C_NSTD

BLANKLVL

_SHIFT_D

ETECTED

INTERLAC

ED_DETE

CTED

DVD_DET

ECTED

VCR_DET

ECTED

INSER_DE

TECTED

FB_DETE

CTED

TRICKMO

D_DETEC

TED

DDECSTAT4

83h

READ ONLY

NOISELVL[7:0]

DDECSTAT5

84h

READ ONLY

SLDID[7:0]

DDECSTAT6

85h

READ ONLY

SLFIL[7:0]

DDECSTAT7

86h

READ ONLY

VBIERR_D

ETECTED

GEM_DET

ECTED

CC_DETE

CTED

VPS_DET

ECTED

WST_DET

ECTED

WSS_DET

ECTED

OPENLOO

DDECSTAT8

Address: 00h

Reset Value (bin): 0000 0100

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VSYNCTYP

PIXMODE

ACTEDGE

CVBSMUX

OUTTRISTA

SVIDEOSEL

5060MODE[1:0]

Bit Name

Function

VSYNCTYPE

Vsync Insertion in Output Flow

The VSYNC output signal is always synchronous to the output clock (CLK_DATA). It will toggle twice per

frame either in Digital or Analog mode according to this option.

0: Analog mode (Interlaced): depends on the standard:

for Output Standard 1: start of line 1 and middle of line 263

for Output Standard 2: start of line 1 and middle of line 313

for Output Standard 3: start of line 1 and middle of line 313 (same as Standard 2)

for Output Standard 4: start of line 1 and middle of line 263 (Default)

1: Digital mode: start of line 1/624 or start of line 264/624 (Vsync at beginning of line)

Note that the analog mode is now split between an "analog output as input" mode and an "analog output

with forced interlaced" output mode. For more information, see bit 3 of register

DDECCONT18.

Name

Add.

(h)

Reset Value

(Bin)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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