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STE2007DIE2 датащи(PDF) 13 Page - STMicroelectronics

номер детали STE2007DIE2
подробное описание детали  96 x 68 Single-chip LCD controller/driver
PDF  62 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE2007DIE2 датащи(HTML) 13 Page - STMicroelectronics

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STE2007
Electrical characteristics
13/62
3.5
Driver TxData mode
Note:
1
Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns
before SCLK pulse falling edge
2
The input signal rise and fall times must be within 10ns.
3
Every timing is specified on the basis of 30% and 70% of VDDI.
Note:
1
The input signal rise and fall times must be within 10ns.
2
Every timing is specified on the basis of 30% and 70% of VDDI.
Table 11.
Input signals change time
Signal
Symbol
Parameter
Min.
Typ.
Max.
Unit
Inputs
tr,tf
(1)
1.
To 30% & 70% levels
10
ns
Table 12.
Timings based on 4 MHz SCLK speed
Symbol
Item
Condition
Min.
Typ.
Max.
Units
T1
Data hold time
Note 1
100
125
ns
T2
Access time
–
10
100
ns
T3
Output disable time
–
25
100
ns
T4
Data setup time
–
100
–
ns
T5
!CS pulse width high
–
250
ns
Table 13.
Timings based on 1 MHz SCLK speed
Symbol
Item
Condition
Min.
Typ.
Max.
Units
T1
Data hold time
–
100
125
ns
T2
Access time
–
10
450
ns
T3
Output disable time
–
25
450
ns
T4
Data setup time
–
100
–
ns
T5
1CS pulse width high
–
250
ns



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