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STE2002DIE2 датащи(PDF) 49 Page - STMicroelectronics

номер детали STE2002DIE2
подробное описание детали  81 x 128 single-chip LCD controller/driver
PDF  61 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE2002DIE2 датащи(HTML) 49 Page - STMicroelectronics

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STE2002
Electrical characteristics
49/61
Serial interface (
Figure 51)
TCYC
Clock Cycle SCLK
VDD1 = 1.7V; Write
(2) (5)
150
ns
TPWH1
SCLK pulse width HIGH
60
ns
TPWL1
SCLK Pulse width LOW
60
ns
TS2
SCE setup time
30
ns
TH2
SCE hold time
50
ns
TPWH2
SCE minimum high time
50
ns
TS3
SD/C setup time
30
ns
TH3
SD/C hold time
40
ns
TS4
SDIN setup time
30
ns
TH4
SDIN hold time
40
ns
TS5
SOUT Access Time
100
ns
TH5
SOUT Disable Time vs.
SCLK
100
ns
TH6
SOUT Disable Time vs.
SCE
100
ns
1.
2.
All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and
VIH with an input voltage swing of VSS to VDD
3.
Cb is the capacitive load for each bus line.
4.
For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5.
CVLCD is the filtering Capacitor on VLCDOUTTrise and Tfall (30%-70%) = 10 ns
Table 27.
AC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
F
frame
f
os
960
--------
=



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