STE2007 datasheet(20/62 Pages) STMICROELECTRONICS

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Interface

STE2007

20/62

4.2

4-Line SPI

STE2007 4-lines serial interface is a bidirectional link between the display driver and the

host processor.

It consists of four lines:

–SDA Serial Data

–

SCL Serial Clock

–

!CS Peripheral enable: - Active Low- Enables and Disables the serial interface

–

Mode selection (D/!C).

The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of

!RES, the serial interface is ready to receive data after the internal reset time.

4.2.1

MCU TxData mode (write mode)

STE2007 is always a slave device on the communication bus and receive the

communication clock on the SCL pin from the master. Information are exchanged byte-wide.

During data transfer, the data line is sampled by the receiver unit on the SCL rising edge.

D/!C line status set whether the byte is a command (D/!C =0) or a data (D/!C =1); D/!C line is

read on the eighth SCL clock pulse during every byte transfer.

If !CS stays low after the last bit of a command/data byte, the serial interface expects the

MSB of the next data byte on the next SCL positive edge.

If !CS line is forced high in the middle of a data transfer, not complete Data bytes and

Commands bytes are discarded.

A reset pulse on !RES pin interrupts any transmission.

Figure 10.

4-lines SPI commands transfe

Figure 11.

4-lines SPI Video data write cycle

LR0189

Hi-Z

COMMAND

D/!C

!CS

SDA

(input)

SCL

SDA

(output)

LR0190

Hi-Z

COMMAND

DATA to VIDEO RAM

D/!C

!CS

SDA

(input)

SCL

SDA

(output)

DATA to VIDEO RAM

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