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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADE3800SXT датащи(PDF) 119 Page - STMicroelectronics |
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ADE3800SXT датащи(HTML) 119 Page - STMicroelectronics |
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119 / 138 page  119/138 ADE3800 Register Description by Block 4.20 Pulse Width Modulation (PWM) The Pulse Width Modulation block generates two signals that can be used to control backlight inverter switching power components directly. It is derived from XCLK and can be powered up independently of the DOTCLK and INCLK domains. The frequency, duty cycle, polarity and overlap/ non-overlap are programmable. The output frequency can be free-running or locked to the output vsync signal. Table 43: PWM Registers (Sheet 1 of 2) Register Name Addr Mode Bits Default Description PWM_CTRL0 01A0 R [7] 00 PWM status 0*: unlocked 1: locked R/W [6] 0*: lock to CYCLES_PER_FRAME from the free-running state machine 1: lock to CYCLES_PER_FRAME register setting R/W [5] PWM_A polarity 0*: active low 1: active high R/W [4] PWM_B polarity 0*: active low 1: active high R/W [3] 0*: normal operation 1: force both PWM outputs to polarity settings of bits 5 and 4 R/W [2] 0*: change period or duty cycle at the end of the current cycle 1: smooth change, period or duty cycle increment/decrement every PWM_STEP_DELAY cycle R/W [1] 0*: free-running 1: lock to out_vsync R/W [0] 0*: disable PWM output 1: enable PWM output PWM_CTRL1 01A1 R/W [7:4] 00 Lock 2 nd order gain (power of 2) 0*: max 3: typical F: min. R/W [3:0] Lock gain (power of 2) 0*: max 6: typical F: min. PWM_PERIOD_L PWM_PERIOD_U 01A2 01A3 R/W R/W [7:0] [7:0] 00 00 Period-2 in free-running mode, in XCLKs PWM_DUTY_L PWM_DUTY_U 01A4 01A5 R/W R/W [7:0] [7:0] 00 00 Duty cycle of PWM in XCLKs PWM_OVERLAP_L PWM_OVERLAP_U 01A6 01A7 R/W R/W [7:0] [7:0] 00 00 Non-overlap of PWMs in XCLKs |
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