| поискавой системы для электроныых деталей |
|
ADE3800SXT датащи(PDF) 115 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ADE3800SXT датащи(HTML) 115 Page - STMicroelectronics |
|
115 / 138 page ![]() 115/138 ADE3800 Register Description by Block ANA_LVDSANA1 0061 [7:6] R/W 00 Bit 3 Data Interface Delay Adjustment, see Bit 0 [5:4] R/W Bit 2 Data Interface Delay Adjustment, see Bit 0 [3:2] R/W Bit 1 Data Interface Delay Adjustment, see Bit 0 [1:0] R/W Bit 0 Data Interface Delay Adjustment 0*: 0ps (normal) 1: 90ps 2: 210ps 3: 460ps ANA_LVDSANA2 0062 [7] C0 PLL power control 0: on 1*: off [6] PLL Global Data Interface Delay 0: no delay 1*: delay (normal) [5:4] R/W Bit 6 Data Interface Delay Adjustment, see Bit 0 [3:2] R/W Bit 5 Data Interface Delay Adjustment, see Bit 0 [1:0] R/W Bit 4 Data Interface Delay Adjustment, see Bit 0 ANA_LVDSANA4 0064 [6:4] R/W 01 LVDS Clock Skew LSB = 135ps (typ) [3] LVDS Clock Skew Enable 0*: no delay (normal) 1: delay [2] LVDSclkout1 output polarity 0*: normal 1: invert [1] LVDSclkout0 output polarity 0*: normal 1: invert [0] LVDS & RSDS Master Power Control (Overrides ANA_LVDSANA5[7], ANA_LVDSANA6[7], and ANA_LVDSANA2[7]) Table 41: LVDS/RSDS Registers (Sheet 2 of 5) Register Name Address Bits Mode Rst Description |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |