STA680Q datasheet(23/43 Pages) STMICROELECTRONICS

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STA680

Operation and general remarks

23/43

4.2

Power on

This chapter describes the power-on procedure for the cold start (cold start means that the

device is completely disconnected from the power supply before being turned on). Figure 8

and Table 4 show the timing for the power up sequence of the cold start.

Figure 8.

Power on timing

4.2.1

Power supply ramp up phase

All power supplies must be ramped-up to their specified levels within the time TRamp-up, set

by the external power supply circuit on the board. The ramp up phase of each power domain

should start at the same time.

The RESET_N pin must be kept low since the beginning. For normal applications, the

TESTMODE pin (Factory test mode enable, see Table 2) must be connected to ground.

Table 4.

Power on timing parameters

Symbol

Parameter

Min

Max

Unit

Tramp-up

External supply ramp-up time

TBD

µs

TDC1V8

DC1V8 regulator start-up time

300

µs

TOSC

Oscillator start-up time

0.18

TRST

Reset release time

1.1

µs

TCFG

Setup of clock/jtag configuration

0.1

µs

Core Clock

DC1V8

OSC

RST

CFG

primary boot

Min @ 2.9184MHz

Max @ 38.48MHz

secondary boot

@ 28.224MHz

functional mode

max @ 166MHz

set for jtag /tap config .

set for clock

config .

Core Supply

(1.2V)

I/Os Supply

(3.3V or 1.8 V)

LDO Input Supply

(3.3V)

LDO Output Supply

(1.8V)

OSC_IN

OSC_OUT

RESET_N

ADAT

ADAT2

ADAT3

BLEND

DAC256X

Ramp - up

AC00708

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