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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LITE1XB датащи(PDF) 70 Page - STMicroelectronics |
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ST7LITE1XB датащи(HTML) 70 Page - STMicroelectronics |
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70 / 159 page  ST7LITE1xB 70/159 DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.7 Force Update In order not to wait for the counterx overflow to load the value into active DCRx registers, a pro- grammable counterx overflow is provided. For both counters, a separate bit is provided which when set, make the counters start with the over- flow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software and re- set by hardware after the respective counter over- flow event has occurred. This feature can be used at any time. All related features such as PWM generation, Output Com- pare, Input Capture, One-pulse (refer to Figure 15. Dynamic DCR2/3 update in One Pulse Mode) can be used this way. Figure 50. Force Overflow Timing Diagram FFF ATRx E04 E03 fCNTRx CNTRx FORCEx FORCE2 FORCE1 ATCSR2 Register 1 |
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