SRI512_08 datasheet(16/47 Pages) STMICROELECTRONICS

16 / 47 page

Memory mapping

SRI512

16/47

Figure 14.

Write_block update in reload mode (binary format)

4.2

32-bit binary counters

The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to

count down from 232 (4096 million) to 0. The SRI512 uses dedicated logic that only allows

the update of a counter if the new value is lower than the previous one. This feature allows

the application to count down by steps of 1 or more. The initial value in the counter is

FFFF FFFFh. When the value displayed is 0000 0000h, the counter is empty and cannot be

reloaded. The counter is updated by issuing the Write_block command to block address 5 or

6, depending on which counter is to be updated. The Write_block command writes the new

32-bit value to the counter block address. Figure 16 shows examples of how the counters

operate.

The counter programming cycles are protected by automated antitearing logic. This function

allows the counter value to be protected in case of power down within the programming

cycle. In case of power down, the counter value is not updated and the previous value

continues to be stored.

Blocks 5 and 6 can be write-protected using the OTP_Lock_Reg bits (block 255). Once a

block has been protected, its contents cannot be modified. A protected counter block

behaves like a ROM block.

Figure 15.

Binary counter (addresses 5 to 6)

ai07659

...11

1011

...11

1011

...11

1011

Previous data stored in block

Data to be written

New data stored in block

b31

Block

Address

MSb

32-bit Block

LSb

Description

Count down

Counter

32-bit Binary Counter

ai12384

b31

b16 b15 b14

b8 b7

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