ISPXPLD5000MX datasheet(6/92 Pages) LATTICE

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Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

AND-Array

The programmable AND-Array consists of 68 inputs and 164 output product terms. The 68 inputs from the GRP are

used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 164 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-

OR Array with the remaining four control product terms feeding the Shared PT Clock, Shared PT Clock Enable,

Shared PT Reset and Shared PT OE. Starting with PT0 sets of ﬁve product terms form product term clusters.

There is one product term cluster for every macrocell in the MFB. In addition to the four control product terms, the

ﬁrst, third, fourth and ﬁfth product terms of each cluster can be used as a PTOE, PT Clock, PT Preset and PT

Reset, respectively. Figure 5 is a graphical representation of the AND-Array.

Figure 5. AND Array

Dual-OR Array (Including Arithmetic Support)

The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the MFB. These OR gates

are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate

receives its ﬁve inputs from the combination of product terms associated with the product term cluster. The PTSA-

Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable PTSA OR gate receives ﬁve

inputs from the combination of product terms associated with the product term cluster. It also receives an additional

input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number of the macrocell associated

with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing with other product terms and

the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for wide functions. There is a

small timing adder for each level of expansion. Figure 6 is a graphical representation of the Dual-OR Array.

The Dual-OR PT sharing array also contains logic to aid in the efﬁcient implementation of arithmetic functions. This

logic takes Carry In and allows the generation of Carry Out along with a SUM signal. Subtractors can be imple-

mented using the two’s complement method. Carry is propagated from macrocells 0 to macrocell 31. Macrocell

zero can have its carry input connected to the carry output of macrocell 31 in an adjacent MFB or it can be set to

zero or one. If a macrocell is not used in an arithmetic function carry can bypass it. The carry chain ﬂows is the

same as that for PT cascading.

PT0

PT1

Cluster 0

PT2

PT3

PT4

In[0]

In[66]

In[67]

Note:

Indicates programmable fuse.

PT160 Shared clock enable

PT162

PT163

Shared reset

Shared OE

PT156

PT157

PT158

PT159

PT155

Cluster 31

PT161 Shared clock

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