RHFL4913

Application information

11/19

parasitic voltage, resistor RW1can be introduced to provide the necessary compensating

voltage signal to the ADJUST pin.

7.3

FPGA power supply lines

supply voltage (usually 1.5 V), special attention must be given by supply lines designers to

mitigate possible heavy ion L4913 disturbances. The worst case heavy ion effect can be

summarized as: the L4913 internal control loop being cut (made open) or short-circuited for

a sub-microsecond duration. During such an event, the L4913 die power element can either

about one microsecond, after which time the L4913 smoothly recovers to nominal operation.

To mitigate these "transients", it is recommended to implement the L4913 PCB layout as

follows:

●

Minimizing series/parallel parasitic inductances of the PC path

●

capacitor in parallel with the former (to reduce dynamic ESR)

●

With this implementation, the ELDO simulated worst transient case shows no more than 90

mV deviation from the nominal line voltage value.