PM6675AS datasheet(19/48 Pages) STMICROELECTRONICS

19 / 48 page

PM6675AS

Device description

19/48

Figure 24.

Switching section simplified block diagram

7.1.2

Output ripple compensation and loop stability

The loop is closed connecting the center tap of the output divider (internally, when the fixed

output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage

mode). The feedback node is the negative input of the error comparator, while the positive

input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback

voltage becomes lower than the reference voltage, the PWM comparator goes high and sets

the control logic, turning on the high-side MOSFET. After the On-Time (calculated as

previously described) the system releases the high-side MOSFET and turns-on the

synchronous rectifier.

The voltage drop along ground and supply PCB paths, used to connect the output capacitor

to the load, is a source of DC error. Further the system regulates the output voltage valley,

not the average, as shown in Figure 22. Thus, the voltage ripple on the output capacitor is

an additional source of DC error. To compensate this error, an integrative network is

introduced in the control loop, by connecting the output voltage to the COMP pin through a

capacitor (CINT) as shown in Figure 25.

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