STM8AF51XX datasheet(49/100 Pages) STMICROELECTRONICS

номер детали	STM8AF51XX

подробное описание детали	Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V

PDF	100 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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49 / 100 page

STM8AF61xx, STM8AF51xx

Option bytes

49/100

Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the

device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection)

byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one

(NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in

Table 12: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP and UBC

options that can only be toggled in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and

debug modulel user manual (UM0470) for information on SWIM programming procedures.

Table 12.

Option bytes

Addr.

Option

name

Option

byte no.

Option bits

Factory

default

setting

4800h

Read-out

protection

(ROP)

OPT0

ROP[7:0]

00h

4801h

User

boot code

(UBC)

OPT1

UBC[7:0]

00h

4802h

NOPT1

NUBC[7:0]

FFh

4803h Alternate

function

remappin

g (AFR)

OPT2

AFR7

AFR6

AFR5

AFR4

AFR3

AFR2

AFR1

AFR0

00h

4804h

NOPT2

NAFR

NAFR5

NAFR4

NAFR3

NAFR2

NAFR1 NAFR0

FFh

4805h

Watchdog

option

OPT3

Reserved

LSI

_EN

IWDG

_HW

WWDG

_HW

WWDG

_HALT

00h

4806h

NOPT3

Reserved

NLSI

_EN

NIWDG

_HW

NWWD

G_HW

NWWG

_HALT

FFh

4807h

Clock

option

OPT4

Reserved

EXT

CLK

CKAWU

SEL

PRS

00h

4808h

NOPT4

Reserved

CLK

NCKAW

USEL

NPR

SC1

NPR

SC0

FFh

4809h HSE

clock

startup

OPT5

HSECNT[7:0]

00h

480Ah

NOPT5

NHSECNT[7:0]

FFh

480Bh

TMU

OPT6

TMU[0:3]

00h

480Ch

NOPT6

NTMU[0:3]

FFh

480Dh

Flash wait

states

OPT7

Reserved

WAIT

STATE

00h

480Eh

NOPT7

Reserved

NWAIT

STATE

FFh

480Fh

Reserved

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