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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDA7580 датащи(PDF) 26 Page - STMicroelectronics |
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TDA7580 датащи(HTML) 26 Page - STMicroelectronics |
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26 / 39 page  Inter processor transport interface for antenna diversity TDA7580 26/39 6 Inter processor transport interface for antenna diversity (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload. The values on the table are consistent with a capacitance load on HS3I lines of 20pF Figure 14. High speed synchronous serial interface - HS3I Figure 15. HS3I clocking scheme Table 20. HS3I timing table Note: TDSP = DSP master clock cycle time = 1/FDSP Timing Description Min Typ Max Unit tsclk MBC clock cycle 107.95 107.97 ns tdtr MBC active edge to master data out valid 4 ns tsetup MBC active edge to master synch valid 4 ns thold Slave data out setup time 6 ns Master Bit Clock Master Data Out Master Synch Slave Data Out M2 M3 S0 S1 S2 S3 256 cycles of 74.1MHz tmbcc tmbco Master Synch Master Data Out Master Bit Clock Slave Data Out tmbcs tsdos |
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