TDA7505 datasheet(32/38 Pages) STMICROELECTRONICS

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Functional description

TDA7505

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in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to

generate the internal clock. This allows the internal clock to be within 1 MHz of any desired

frequency even when XTI is much greater than 1 MHz. It is recommended that the input

clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update

rate.

The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be

driven by the XTI pin directly.

The crystal oscillator and the PLL will be gated off when entering the power-down mode (by

setting a register on DSP0).

5.2.12

CODEC

The CODEC is composed of four plus one A/D mono converters and three D/A stereo

converters.

Two channels of the ADC can operate both in audio mode and in FM mode. When in audio

mode, it converts the audio bandwidth from 20Hz to 20KHz. The A to D is a third order

Sigma-Delta converter with 20-bit resolution. When in FM mode, the converted bandwidth is

up to 192KHz.

Additionally a lower resolution A to D converter is implemented. It is used to convert the

level signal of the tuner. Alternatively it may be used to convert voice signals.

The DAC is a second order multi bits Sigma-Delta converter accepting 24 bits input data. All

the reference voltages are generated inside the chip but they have to be decoupled with

external capacitors.

5.2.13

Radio data system (RDS)

The RDS block is a hardware cell able to deliver the RDS frames through a dedicated serial

interface. An RDS quality signal is also available. This block needs to be initialized at reset

by the DSP, after that it works in background and does not need any further DSP support.

RDS is made of 57kHz filter, demodulator, decoder with error correction and an I2C/SPI

programmable interface with data buffer and interrupt output.

Due to its own interface, it may be considered as an independent function. Thus the module

has a separate RDS I2C device address as well as a separate chip select line for the RDS

SPI. Only the pins are shared with the DSP interfaces.

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