M48T58Y-70MH1 datasheet(11/31 Pages) STMICROELECTRONICS

номер детали	M48T58Y-70MH1

подробное описание детали	5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM

PDF	31 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

Logo

11 / 31 page

M48T58, M48T58Y

Write mode

11/31

Write mode

The M48T58/Y is in the WRITE Mode whenever W and E1 are low and E2 is high. The start

of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge

of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.

The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low

for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE Enable prior to

the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end

of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles

to avoid bus contention; although, if the output bus has been activated by a low on E1 and G

and a high on E2, a low on W will disable the outputs tWLQZ after W falls.

Figure 6.

Write enable controlled, write AC waveform

AI00963

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVWH

tAVE1L

tAVE2H

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

M48T58Y-70MH1 датащи(PDF) 11 Page - STMicroelectronics