M48T58, M48T58Y

Clock operations

19/31

Note:

This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is

disconnected.

Note:

Battery monitoring is a useful technique only when performed periodically. The M48T58/Y

which require extensive durations in the battery back-up mode should be powered-up

periodically (at least once every few months) in order for this technique to be beneficial.

Additionally, if a battery low is indicated, data integrity should be verified upon power-up via

a checksum or other technique.

6.6

Century bit

Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the

CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

Note:

The WRITE Bit must be set in order to write to the CENTURY Bit.

6.7

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A bypass capacitor value of 0.1µF (as shown in

Figure 10) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, it is recommended to connect a

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface

mount.

Figure 10.

Supply voltage protection

AI02169

VCC

0.1

μF

DEVICE

VCC

VSS