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3.9 INPUT CAPACITOR

The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle

as reported in Figure 15. Considering the two-phase topology, the input RMS current is highly reduced

comparing with a single-phase operation.

It can be observed that the input RMS value is one half of the single-phase equivalent input current in the

worst case condition that happens for D=0.25 and D=0.75.

The power dissipated by the input capacitance is then equal to:

Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach

the RMS value needed and also to minimize components cost, the input capacitance is realized by more

than one physical capacitor. The equivalent RMS current is simply the sum of the single capacitor's RMS

current.

Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as pos-

sible to reduce switching noise above all during load transient. Ceramic capacitor can also introduce ben-

efits in high frequency noise de coupling, noise generated by parasitic components along power path.

Figure 15. Input RMS Current vs. Duty Cycle (D) and Driving Relationships.

3.10 OUTPUT CAPACITOR

The output capacitor is a basic component for the fast response of the power supply.

Two-phase topology reduces the amount of output capacitance needed because of faster load transient

response (switching frequency is doubled at the load connections). Current ripple cancellation due to the

180° phase shift between the two phases also reduces requirements on the output ESR to sustain a spec-

ified voltage ripple.

Moreover, if DROOP function is enabled, bigger ESR can be used still keeping the same transient toler-

ances. In fact, when a load transient is applied to the converter's output, for first few microseconds the

current to the load is supplied by the output capacitors. The controller recognizes immediately the load

transient and increases the duty cycle, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect

of the ESL):

A minimum capacitor value is required to sustain the current during the load transient without discharge

P

RMS

ESR

I

RMS

()

2

⋅

=

0.50

0.75

0.25

0.50

0.25

Single Phase

Dual Phase

I

rms

I

OUT

2

------------

2D

1

2D

–

()

⋅

if

D < 0.5

⋅

I

OUT

2

------------

2D

1

–

() 22D

–

()

⋅

if

D > 0.5

⋅

⎩

⎪

⎪

⎨

⎪

⎪

⎧

=

∆V

OUT

∆I

OUT

ESR

⋅

=