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November 2004

s

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 27

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC27 is an advanced high-speed CMOS

TRIPLE 3-INPUT NOR GATE fabricated with

sub-micron silicon gate and double-layer metal

The internal circuit is composed of 3 stages

including buffer output, which provides high noise

immunity and stable output.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74VHC27

TRIPLE 3-INPUT NOR GATE

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHC27MTR

TSSOP

74VHC27TTR

TSSOP

SOP

Rev. 4