LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
13 of 70
NXP Semiconductors
LPC1766
Fast communication chip
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
P4[29]/TX_MCLK/
MAT2[1]/RXD3
85[1]
I/O
P4[29] — General purpose digital input/output pin.
I
TX_MCLK — I2S transmit master clock.
O
MAT2[1] — Match output for Timer 2, channel 1.
I
RXD3 — Receiver input for UART3.
TDO/SWO
1[1]
O
TDO — Test Data out for JTAG interface.
O
SWO — Serial wire trace output.
TDI
2[1]
I
TDI — Test Data in for JTAG interface.
TMS/SWDIO
3[1]
I
TMS — Test Mode Select for JTAG interface.
I/O
SWDIO — Serial wire debug data input/output.
TRST
4[1]
I
TRST — Test Reset for JTAG interface.
TCK/SWDCLK
5[1]
I
TCK — Test Clock for JTAG interface.
I
SWDCLK — Serial wire clock.
RTCK
100[1]
I/O
RTCK — JTAG interface control signal.
RSTOUT
14
O
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC1766 being in Reset
state.
RESET
17[7]
I
External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
22[8]
I
Input to the oscillator circuit and internal clock generator circuits.
XTAL2
23[8]
O
Output from the oscillator amplifier.
RTCX1
16[8]
I
Input to the RTC oscillator circuit.
RTCX2
18[8]
O
Output from the RTC oscillator circuit.
VSS
31, 41,
55, 72,
97, 83[8]
I
ground: 0 V reference.
VSSA
11[8]
I
analog ground: 0 V reference. This should nominally be the same voltage as VSS,
but should be isolated to minimize noise and error.
VDD(3V3)
28, 54,
71, 96[8]
I
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
VREG(3V3)
42, 84[8]
I
3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip
voltage regulator only.
VDDA
10[8]
I
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC.
VREFP
12[8]
I
ADC positive reference voltage: This should be nominally the same voltage as
VDDA but should be isolated to minimize noise and error. Level on this pin is used
as a reference for ADC and DAC.
VREFN
15
I
ADC negative reference voltage: This should be nominally the same voltage as
VSS but should be isolated to minimize noise and error. Level on this pin is used as
a reference for ADC and DAC.
VBAT
19[8]
I
RTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
n.c.
13
-
not connected
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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