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STLC5460 датащи(PDF) 39 Page - STMicroelectronics |
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STLC5460 датащи(HTML) 39 Page - STMicroelectronics |
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39 / 54 page ![]() RCM Subchannel select 01 and data rate 1 of 192 input timeslots 1 of 2 insert registers 1 of 192 output timeslots 1 of 2 extract registers CMD SRC DST Command Memory 194 words of 14 bits A IN IN 6 88 R=0 Write CM=1 Command Memory APPENDIX MEMORY ACCESSES COMMAND MEMORY ACCESSES. CM=1 Write Command Memory: CMD and SRC registers are written if their bits have not the right value. CMD and SRC registers can be written in any order. DST register is always written the last Read Command Memory in two steps: First step: register writing CMD register is written if its bits are not the right value. SRC register is not written. DST register is always written the last. R CM bits not used 1 1 Register not written 1 of 192 output timeslots 1 of 2 extract register CMD SRC DST Command Memory 194 words of 14 bits A OUT OUT R CM selected channel 1 1 and data rate 1 of 192 input timeslots 1 of 2 insert registers 1 of 192 output timeslots 1 of 2 extract register s CMD SRC DST 8 8 6 2 Second step: register reading: CMD and SRC registers may be read in any order. DST register is not changed. STLC5460 39/54 |
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