STLC1511

16/31

3.4.3 Customer Premise Equipment

In CPE mode, the STLC1511 provides the amplifier

required to power the off-chip crystal oscillator. The

crystal oscillator runs at a frequency of 35.328 MHz

(series resonant) which is further divided down to

provide the sampling clocks to both the TX and RX

converters and passed to the STLC1510 as its PLL

reference on the pin DIGREF. Note that in CPE

mode, neither the PLL or the pin FREF is used (FREF

should be connected to either Vdd or Vss) and that

the tuing for the external oscillator is generated on

the STLC1510.

The following table details the CPE oscillator perfor-

mance when connected as shown in Figure 3. on

page 14. CPE mode is selected by setting b5:b0 in

register “AFE Control 5” to “001110”. See section

"Digital Interface And Memory Map" on page 20 for

more information.

Note the reference design provided is based on a

Reeves Hoffman fundamental Mode AT cut crystal at

35.328MHz.(Crystal accuracy@+/-50ppm (+/-15ppm

calibration tolerance, +/-15ppm 10 year aging, +/-20

ppm

temperature

variation,

Rs@15

Ω

max,

Cm@15fF max, and Co@3.5pF typ (assumes a

HC49/43 package).)

Table 6. CPE PLL Specifications

Unless otherwise noted, typical specifications apply for VCC=5.0 V, temperature = 25×C, nominal process and bias

Description

min

typ

max

Units

Comments

Output Clock Frequency

35.328

MHz

at pin DIGREF

-50

+50

ppm

crystal accuracy for CPE.

Crystal Frequency Tuning

-125

+125

ppm

Occurs at CPE. Assumes

CO is free running

Oscillator Signal Level

200

500

mVp

Power Up Time

5

10

msec

VCO Gain

Vcxo gain (crystal)

1.4

1.6

1.7

KHz/V

see TITLE 2 3.5 on page 18

Input Impedance @OSCPB

see TITLE 3 3.4.3 on page

16

Output Impedance @OSCPE

see TITLE 3 3.4.3 on page

16

5

10Hz offset

20Hz offset

40Hz offset

60Hz offset

80Hz offset

100Hz offset

200Hz offset

400Hz offset

600Hz offset

800Hz offset

1000Hz offset

-51.9

-57.9

-63.9

-67.5

-69.9

-71.9

-77.9

-83.9

-87.5

-89.9

-91.9

dBc/Hz

Phase noise at DIGREF

output (i.e. 35.328MHz) in

CPE mode.

<1>For the CPE side a crystal oscillator will be used.

<2>50ppm accuracy is divided as ±15ppm for manufacture, ± 15ppm for 10 year drift, and ± 20ppm for temperature variation.

<3>Worst case for tuning is when CO is not locked and CPE must retime from CO. Nominally the tuning range for the CO is ±50ppm,

so that if the CO is free running, the CPE must tune over the CO inaccuracy and the CPE crystal inaccuracy as well.

<4>Input and output impedance measured with 50kW from OSCPB to Vcc and OSCNB to Vcc

<5>For inband noise, phase noise at multiples of 4.3125kHz will rms add to degrade the inband SNR. Similarly, for out of band signals,

phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the SNR. For example,

noise contributions on carriers from 34 to 127 will rms add to degrade the SNR on the edge of the US band (carrier 26).