TPD4E004DRLR datasheet(6/12 Pages) TI

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APPLICATION INFORMATION

IO3

IO4

GND

IO2

IO1

0.1 µF

USB

Controller

BUS

D+

D–

GND

BUS

D+

D–

GND

Detailed Description

TPD4E004

4-CHANNEL ESD-PROTECTION ARRAY

FOR HIGH-SPEED DATA INTERFACES

SLVS729A – FEBRUARY 2008 – REVISED FEBRUARY 2008

When placed near the connector, the TPD4E004 ESD solution offers little or no signal distortion during normal

operation due to low I/O capacitance and ultra-low leakage current specifications. The TPD4E004 ensures that

the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper

operation, the following layout/design guidelines should be followed:

1. Place the TPD4E004 solution close to the connector. This allows the TPD4E004 to take away the energy

associated with ESD strike before it reaches the internal circuitry of the system board.

2. Place a 0.1-

µF capacitor very close to the V

CC pin. This limits any momentary voltage surge at the IO pin

during the ESD strike event.

3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the

TPD4E004 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 µA to 30 µA

of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy

associated with the ESD strike.

4. Leave the unused IO pins floating.

5. The VCC pin can be connected in two different ways:

If the VCC pin is connected to the system power supply (a 0.1-µF capacitor at VCC is recommended for

ESD bypass), the TPD4E004 works as a transient voltage suppressor for any signal swing above VCC +

Vd.

If the VCC pin is not connected to system power supply (a 0.1-µF capacitor is still recommended at the

VCC pin for ESD bypass), the TPD4E004 can tolerate higher signal swing in the range up to VBR. Note

that initially the bypass capacitor is charged by the signals through clamp diode.

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