R8051XC Configurable Microcontroller
Configurable Microcontroller
Copyright © 2005 - 2008 Evatronix SA
R8051XC-DSN-1HV28F26S00-200
Page 7 of 8
Verification Methods
The core has been verified through extensive simulation and
rigorous code coverage measurements. All subcomponents
were functionally verified with an HDL testbench using their
individual test suites. The CPU and ALU have been verified
against a proprietary hardware modeler and behavioral
models. The peripherals have also been verified in their own
testbenches, based on either hardware or behavioral models.
The core satisfies the requirements of the Reuse Methodology
Manual and the VSIA Quality IP Metric.
Quality IP Assessment
Score
IP Ease of Reuse
97%
Design & Verification Quality
83%
IP Maturity
100%
Vendor Assessment
82%
Total
89%
The R8051XC has been verified through extensive functional
simulation and it has achieved high Code Coverage simulation
results.
Code Coverage
Metric
Statement
100 %
Branch
96.7 %
Condition
80.5 %
Triggering
-
Path
62.9 %
Toggle
93.1 %
The trial ATPG coverage figures met the requirements and
reached level of 99%. Additionally the value of IDDQ reached
level of 99%.
Related Products
SPI-MS - Serial Peripheral Interface supporting slave as well
as
master
capability
with
own
rate
generator
and
programmable polarity of serial clock. A dedicated set of slave
selection signals facilitates integration in multi slave system;
I2C – controller which meets the original Philips I2C bus
interface controller specification requirements. It may operate
in
one
of
the
following
transmission
modes:
Master
Transmitter, Master Receiver, Slave Transmitter and Slave
Receiver with transmission rates up to 400 kHz;
I2CS – controller compatible with the Philips I2C bus interface
slave controller. It may operate in one of the following
transmission modes: Slave Transmitter and Slave Receiver with
transmission rates up to 400 kHz.
Third Party Reference
The
R8051XC
core
may
be
delivered
with
debug
instrumentation implemented and ready to work with Keil
uVision debug environment. For more details about On Chip
Debug
Support
visit
Evatronix
web
site
http://www.evatronix.pl.
Following is a link to the R8051XC on the list of devices that
are
supported
by
the
Keil
development
tools
http://www.keil.com/dd/chip/4122.htm.
Pin Description – Continued
*The OCI and OCDS are mutually exclusive
Name
Type
Polarity/
Bus size
Description
Trace RAM signals (OCDS)*
addr_buf0
O
4
Trace buffer 0 address bus
addr_buf1
O
4
Trace buffer 1 address bus
datao_buf0
O
45
Trace buffer 0 data output
datao_buf1
O
45
Trace buffer 1 data output
datai_buf0
I
45
Trace buffer 0 data input
datai_buf1
I
45
Trace buffer 1 data input
wr_buf0
O
High
Trace buffer 0 write enable
wr_buf1
O
High
Trace buffer 1 write enable
rd_buf0
O
High
Trace buffer 0 read enable
rd_buf1
O
High
Trace buffer 1 read enable
Hold interface
hold
I
High
Hold mode request
holda
O
High
Hold mode acknowledge signal
intoccur
O
High
Interrupt occured in Hold mode
I2C™ interface
scli
I
High
I2C serial clock input
sclo
O
High
I2C serial clock output
sdai
I
-
I2C data input
sdao
O
-
I2C data output
Secondary I2C™ interface
scl2i
I
High
I2C serial clock input
scl2o
O
High
I2C serial clock output
sda2i
I
-
I2C data input
sda2o
O
-
I2C data output
SPI interface
ssn
I
Low
SPI Slave Select input
misoi
I
-
SPI Master Input / Slave Output
bidirectional port – input part
misoo
O
-
SPI Master Input / Slave Output
bidirectional port – output part
misotri
O
High
SPI Master Input / Slave Output
bidirectional port – output enable
mosii
I
-
SPI Master Output / Slave Input
bidirectional port – input part
mosio
O
-
SPI Master Output / Slave Input
bidirectional port – output part
mositri
O
High
SPI Master Output / Slave Input
bidirectional port – output enable
scki
I
Rise/Fall
SPI Serial Clock bidirectional port
– input part
scko
O
Rise/Fall
SPI Serial Clock bidirectional port
– output part
scktri
O
High
SPI Serial Clock bidirectional port
– output enable
spssn
O
8
8-bit output port to control
external slave devices
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