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are trademarks of their respective owners.

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Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

microcontroller is planned to use in portable

and power critical applications.

DoCD™ Debug Unit

– it’s a real-time hard-

ware debugger provides debugging capability

of a whole SoC system. In contrast to other on-

chip debuggers DoCD™ provides non-intrusive

debugging of running application. It can halt,

run, step into or skip an instruction, read/write

any contents of microcontroller including all

registers, internal, external, program memo-

ries, all SFRs including user defined peripher-

als. Hardware breakpoints can be set and con-

trolled on program memory, internal and exter-

nal data memories, as well as on SFRs. Hard-

ware breakpoint is executed if any write/read

occurred at particular address with certain data

pattern or without pattern. The DoCD™ system

includes three-wire interface and complete set

of tools to communicate and work with core in

real time debugging. It is built as scalable unit

and some features can be turned off to save

silicon and reduce power consumption. A spe-

cial care on power consumption has been

taken, and when debugger is not used it is

automatically switched in power save mode.

Finally whole debugger is turned off when de-

bug option is no longer used.

PERFORMANCE

The following tables give a survey about the

Core area and performance in ASICs Devices

(all CPU features and peripherals have been

included):

Device

Optimization

0.25u typical

area

100 MHz

0.25u typical

speed

250 MHz

Core performance in ASIC devices

For a user the most important is application

speed improvement. The most commonly used

arithmetic functions and their improvements

are shown in table below. An improvement was

computed as {80C51 clock periods} divided by

{DR8051CPU clock periods} required to exe-

cute an identical function. More details are

available in core documentation.

Function

Improvement

8-bit addition (immediate data)

7,20

8-bit addition (direct addressing)

6,00

8-bit addition (indirect addressing)

6,00

8-bit addition (register addressing)

7,20

8-bit subtraction (immediate data)

7,20

8-bit subtraction (direct addressing)

6,00

8-bit subtraction (indirect addressing)

6,00

8-bit subtraction (register addressing)

7,20

8-bit multiplication

10,67

8-bit division

9,60

16-bit addition

7,20

16-bit subtraction

7,64

16-bit multiplication

9,75

32-bit addition

7,20

32-bit subtraction

7,43

32-bit multiplication

9,04

Average speed improvement:

7,58

Dhrystone Benchmark Version 2.1 was used to

measure Core performance. The following ta-

ble gives a survey about the DR8051CPU per-

formance in terms of Dhrystone/sec and VAX

MIPS rating.

Device

Target

Clock

frequency

Dhry/sec

(VAX MIPS)

80C51

-

12 MHz

268 (0.153)

80C310

-

33 MHz

1550 (0.882)

DR8051CPU

0.25u

250 MHz 40325 (22.951)

Core performance in terms of Dhrystones

268

1550

40325

0

5000

10000

15000

20000

25000

30000

35000

40000

45000

80C51 (12MHz)

80C310 (33MHz)

DR8051CPU (250MHz)

Area utilized by the each unit of DR8051CPU

core in vendor specific technologies is summa-

rized in table below.

Area

Component

[Gates]

[FFs]

CPU*

4850

220

Interrupt Controller

400

40

Power Management Unit

50

5

Total area

5300

265

*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &

Internal & External Memory Interfaces, User SFRs Interface

Core components area utilization