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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DR80390CPU датащи(PDF) 2 Page - Digital Core Design |
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DR80390CPU датащи(HTML) 2 Page - Digital Core Design |
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2 / 7 page  All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. ● Fully synthesizable, static synchronous de- sign with positive edge clocking and no in- ternal tri-states ● Scan test ready ● 1.3 GHz virtual clock frequency in a 0.35u technological process PERIPHERALS ● DoCD™ debug unit ○ Processor execution control ○ Run ○ Halt ○ Step into instruction ○ Skip instruction ○ Read-write all processor contents ○ Program Counter (PC) ○ Program Memory ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Hardware execution breakpoints ○ Program Memory ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Hardware breakpoints activated at a certain ○ Program address (PC) ○ Address by any write into memory ○ Address by any read from memory ○ Address by write into memory a required data ○ Address by read from memory a required data ○ Three wire communication interface ● Power Management Unit ○ Power management mode ○ Switchback feature ○ Stop mode ● Interrupt Controller ○ 2 priority levels ○ 2 external interrupt sources CONFIGURATION The following parameters of the DR80390CPU core can be easy adjusted to requirements of dedicated application and technology. Configu- ration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. - Harward • Memory style - von Neumann - synchronous • Program Memory type - asynchronous - used (0-7) • Program Memory wait- states - unused - used • Program Memory writes - unused - synchronous • Internal Data Memory type - asynchronous - used (0-7) • External Data Memory wait-states - unused • Interrupts - subroutines location - used • Power Management Mode - unused - used • Stop mode - unused - used • DoCD debug unit - unused DELIVERABLES ♦ Source code: ◊ VHDL Source Code or/and ◊ VERILOG Source Code or/and ◊ Encrypted, or plain text EDIF netlist ♦ VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses ♦ Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet ♦ Synthesis scripts ♦ Example application ♦ Technical support ◊ IP Core implementation support ◊ 3 months maintenance ● Delivery the IP Core updates, minor and major versions changes ● Delivery the documentation updates |
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