AT91SAM9263 datasheet(13/48 Pages) ATMEL

13 / 48 page

6249BS–ATARM–18-Dec-06

AT91SAM9263 Preliminary

• VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V to 3.6V, L3.3V

nominal.

The power supplies VDDIOM0, VDDIOM1 and VDDIOP0, VDDIOP1 are identified in the pinout

table and the multiplexing tables. These supplies enable the user to power the device differently

for interfacing with memories and for interfacing with peripherals.

Ground pins GND are common to VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 and

VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU and VDDPLL.

These ground pins are respectively GNDBU and GNDPLL.

5.2

Power Consumption

The AT91SAM9263 consumes about 700 µA of static current on VDDCORE at 25°C. This static

current rises at up to 7 mA if the temperature increases to 85°C.

On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C. A

software-controllable switch to VDDCORE guarantees zero power consumption on the battery

when the system is on.

For dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 mA on

VDDCORE at maximum conditions (1.2V, 25°C, processor running full-performance algorithm).

5.3

Programmable I/O Lines Power Supplies

The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the

device to reach its maximum speed, either out of 1.8V or 3.0V external memories.

The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power

supply at 1.8V and 50pF for power supply at 3.3V. The other signals (control, address and data

signals) do not go over 50MHz.

The voltage ranges are determined by programming registers in the Chip Configuration registers

located in the Matrix User Interface.

At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either

1.8V or 3.3V. However, the device cannot reach its maximum speed if the voltage supplied to

the pins is only 1.8V without reprogramming the EBI0 voltage range. The user must be sure to

program the EBI0 voltage range before getting the device out of its Slow Clock Mode.

I/O Line Considerations

6.1

JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level

(VDDBU). It integrates a permanent pull-down resistor of about 15 k

Ω to GNDBU, so that it can

be left unconnected for normal operations.

The NTRST signal is described in Section 6.3.

All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.

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