AD7264BSTZ datasheet(22/32 Pages) AD

22 / 32 page

AD7264

Rev. A | Page 22 of 32

ON-CHIP REGISTERS

The AD7264 contains a control register, two offset registers for

storing the offsets for each ADC, and two external gain registers

for storing the gain error. The control, offset, and gain registers

are read and write registers. On power-up, all registers in the

AD7264 are set to 0 by default.

Writing to a Register

Data is loaded from the PD0/DIN pin of the AD7264 on the

falling edge of SCLK when CS is in a logic low state. Four

address bits and 12 data bits must be clocked into the device.

Thus, on the 16th falling SCLK edge, the LSB is clocked into the

AD7264. One more SCLK cycle is then required to write to the

internal device registers. In total, 17 SCLK cycles are required to

successfully write to the AD7264. The control and offset

registers are 12-bits registers, and the gain registers are 7-bit

registers.

When writing to a register, the user must first write the address

bits corresponding to the selected register. Table 11 shows the

decoding of the address bits. The four RD bits are written MSB

first, that is, RD3 followed by RD2, RD1, and RD0. The AD7264

decodes these bits to determine which register is being addressed.

The subsequent 12 bits of data are written to the addressed register.

When writing to the external gain registers, the seven bits of

data immediately after the four address bits are written to the

PD0/DIN pin of the AD7264 should be tied low for the five

additional clock cycles.

Table 11. Read and Write Register Addresses

RD3

RD2

RD1

RD0

Comment

ADC result (default)

Control register

Offset ADC A internal

Offset ADC B internal

Gain ADC A external

Gain ADC B external

Reading from a Register

The internal offset of the device, which has been measured by

the AD7264 and stored in the on-chip registers during the

calibration, can be read back by the user. The contents of the

external gain registers can also be read. To read the contents of

any register, the user must first write to the control register by

writing 0001 to the WR3 to WR0 bits via the PD0/DIN pin (see

Table 10). The next four bits in the control register are the RD

bits, which are used to select the desired register from which to

read. The appropriate 4-bit addresses for each of the offset and

gain registers are listed in Table 11. The remaining eight SCLK

cycle bits are used to set the remaining bits in the control

The 19th SCLK falling edge clocks out the first data bit of the

digital code corresponding to the value stored in the selected

internal device register on the DOUTA pin. DOUTB outputs the

conversion result from ADC B. When the selected register has

been read, the control register must be reset to output the ADC

results for future conversions. This is achieved by writing 0001

to the WR3 to WR0 bits, followed by 0000 to the RD bits. The

remaining eight bits in the control register should then be set to

the required configuration for the next ADC conversion.

SCLK

DOUTA

PD0/DIN

THREE-STATE

THREE-

STATE

DB12A

DB13A

DB0A

THREE-STATE

RD1

RD0

MSB

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

RD2

RD3

QUIET

t13

t14

Figure 31. Timing Diagram for Writing to a Register

SCLK

DOUTA

PD0/DIN

THREE-STATE

THREE-

STATE

DB12A

DB13A

DB0A

THREE-STATE

RD3

RD2

RD1

RD0

t13

t14

tQUIET

Figure 32. Timing Diagram for a Read Operation with PD0/DIN as an Input

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