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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OMAP3530 датащи(PDF) 17 Page - Texas Instruments |
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OMAP3530 датащи(HTML) 17 Page - Texas Instruments |
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17 / 264 page  OMAP3530/25 Applications Processor www.ti.com SPRS507B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BALL PIN MODE [4] TYPE [5] BALL BALL RESET POWER [9] HYS BUFFER PULL IO BOTTOM [1] TOP [2] NAME [3] RESET RESET REL. [10] STRENGTH U/D CELL [13] STATE [6] REL. MODE [8] (mA) [11] TYPE STATE [7] [12] D3 V22 sdrc_a10 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D2 V23 sdrc_a11 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D1 W22 sdrc_a12 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E2 W23 sdrc_a13 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E1 Y22 sdrc_a14 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H11 M22 sdrc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H12 M23 sdrc_ncs1 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A13 A11 sdrc_clk 0 IO L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A14 B11 sdrc_nclk 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H16 J22 sdrc_cke0 0 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode 7 H17 J23 sdrc_cke1 0 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode 7 H14 L23 sdrc_nras 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H13 L22 sdrc_ncas 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H15 K23 sdrc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS B7 C1 sdrc_dm0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A16 A17 sdrc_dm1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B11 A6 sdrc_dm2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C20 A20 sdrc_dm3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A6 C2 sdrc_dqs0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A17 B17 sdrc_dqs1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A10 B6 sdrc_dqs2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A20 B20 sdrc_dqs3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS N4 AC15 gpmc_a1 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 M4 AB15 gpmc_a2 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 L4 AC16 gpmc_a3 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 K4 AB16 gpmc_a4 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 T3 AC17 gpmc_a5 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 R3 AB17 gpmc_a6 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 N3 AC18 gpmc_a7 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 M3 AB18 gpmc_a8 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 L3 AC19 gpmc_a9 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq2 1 I gpio_42 4 IO safe_mode 7 K3 AB19 gpmc_a10 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq3 1 I Submit Documentation Feedback TERMINAL DESCRIPTION 17 |
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